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30 SEATS

COURSE INSTRUCTOR

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Venkat

VLSI Designer

More than 5 Years Expert in VLSI.

BASIC INFORMATION

  • Lessons : 07
  • Length : 6 Months
  • Level : Basic
  • Category : Software Training
  • Started : 01-05-2019
  • Shift : 02
  • Class : 120

VLSI Training and Course Description

VLSI or Very Large Scale Integration is a way through which integrated circuit is created by integrating millions of transistors into a single chip. This design has become the most happening field of electronics and is finding its application in diverse range of electrical equipment like computer peripherals, cell phones, satellites, defense aerospace, consumer electronics, set top entertainment boxes and several other devices. All those candidates, who are looking to build a career in VLSI field, Vector Institute offers training program in VLSI technologies, which is designed to meet the contemporary demands of the industry. Our VLSI technologies course trained candidates with various domains of chip design. Our training course on VLSI technologies is the right blend of classroom teaching, hands-on experience and workplace dynamics. The candidates undergo this training through classroom teaching and practical classes in the initial training program, which is followed by industry-driven projects in the next training program. After successfully completing the training program that candidate become proficient and job ready in diverse areas of VLSI Logic and Physical design. The entire VLSI training program is designed in such a manner that candidates well understand the concepts and get good overview of the design requirements. Our VLSI Design Course imparts ASIC, FPGA design flows, and trains engineers extensively on the VLSI design methodologies, CMOS, VHDL, Verilog and System Verilog. An unprecedented demand for the expert professionals of VLSI Design is encouraging us to offer course that geared towards meeting the increasing demand of the electronic industry.

VLSI Training and Course Syllabus

Module 1: ASIC / FPGA DESIGN

  • ASIC / FPGA Design Fundamentals
  • Advanced Digital Design
  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for NMOS/PMOS/CMO
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals
  • VHDL Overview and Concepts
  • Levels of Abstraction
  • Entity, Architecture
  • Data Types and declaration
  • Relational, Logical, Arithmetic Operators
  • Signal and Variables, Constants
  • Process Statement
  • Concurrent Statements
  • When-else, With-select
  • Sequential Statement
  • If-then-else, Case
  • Slicing and Concatenation
  • Loop Statements
  • Delta Delay Concept
  • Arrays, Memory Modeling, FSM
  • Writing Procedures
  • Writing Functions
  • Behavioral / RTL Coding
  • Operator Overloading
  • Structural Coding
  • Component declarations and installations
  • Generate Statement
  • Configuration Block
  • Libraries, Standard packages
  • Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Assertion based verification
  • Files read and write operations
  • Code for complex FPGA and ASICs
  • Generics and Generic maps
  • Language introduction
  • Levels of abstraction
  • Module, Ports types and declarations
  • Registers and nets, Arrays
  • Identifiers, Parameters
  • Relational, Arithmetic, Logical, Bit-wise shift Operators
  • Writing expressions
  • Behavioral Modeling
  • Structural Coding
  • Continuous Assignments
  • Procedural Statements
  • Always, Initial Blocks, begin ebd, fork join
  • Blocking and Non-blocking statements
  • Operation Control Statements
  • If, case
  • Loops: while, for-loop, for-each, repeat
  • Combination and sequential circuit designs
  • Memory modeling, state machines
  • CMOS gate modeling
  • Writing Tasks
  • Writing Functions
  • Compiler directives
  • Conditional Compilation
  • System Tasks
  • Gate level primitives
  • User defined primitives
  • Delays, Specify block
  • Testbenchs, modeling, timing checks
  • Assertion based verification
  • Code for synthesis
  • Advanced topics
  • Writing reusable code
  • Introduction to System Verilog
  • System Verilog Declaration spaces
  • System Verilog Literal Values and Built-in Data Types
  • System Verilog User-Defined and Enumerated Types
  • System Verilog Arrays, Structures and Unions
  • System Verilog Procedural Blocks, Tasks and Function
  • System Verilog Procedural Statements
  • Modelling Finite State Machines with System Verilog
  • System Verilog Design Hierarchy
  • System Verilog Interfaces
  • Behavioral and Transaction Level Modelling
  • Re-configurable Devices, FPGA’s/CPLD’s
  • Architectures of XILINX, ALTERA Devices
  • Designing with FPGAs
  • FPGA’s and its Design Flows
  • Architecture based coding
  • Efficient resource utilization
  • Constrains based synthesis
  • False paths and multi cycle paths
  • UCF file creation
  • Timing analysis/Floor Planning
  • Place and route/RPM
  • Back annotation, Gate level simulation, SDF Format
  • DSP on FPGA
  • Writing Scripts
  • Hands on experience with industry Standard Tools
  • EDA Tools / CAD Flow for IC Design
  • Simulation/Synthesis using ASIC libraries
  • Clock Tree Synthesis
  • False paths / Multi cycle paths / Critical paths
  • Design for Testability (DFT)
  • Scan Insertion / Types of Scan
  • Fault Models
  • Logic BIST, Memory BIST, ATGP, Boundary Scan
  • Pattern Compression
  • Scan Diagnostics
  • Layout Design
  • Placing and Routing
  • LVS/DRC/OPC/Physical verificationn
  • Diagnosis, DFM, Yield Analysis
  • SOC Design and Trade-offs
  • Future Trends and challenges
  • ASIC Case Studies